C200 datasheet(55/82 Pages) INTEL

55 / 82 page

Specification Update

Documentation Changes

13.

Auxiliary Trip Point Lock Bit Correction

Section 22.2.5 TSTTP—Thermal Sensor Temperature Trip Point Register bits 23:16 are

changed as shown:

14.

Top Swap Updates

a. Section 10.1.44 BUC—Backed Up Control Register bit 0 is changed as shown:

b. BOOT_BLOCK_SIZE soft strap name is changed to BIOS Boot-Block size soft strap.

c. Table 2-27 is updated as shown:

Bit

Description

23:16

Auxiliary Trip Point Setting (ATPS) — R/W. These bits set the Auxiliary trip point.

These bits are lockable using programming the policy-lock down bit (bit 7) of TSPC

These bits may only be programmed from 0h to 7Fh. Setting bit 23 is not supported.

Bit

Description

Top Swap (TS) — R/W.

0 = PCH will not invert A16.

1 = PCH will invert A16, A17, or A18 for cycles going to the BIOS space.

If booting from LPC (FWH), then the boot-block size is 64 KB and A16 is inverted if

Top Swap is enabled.

If booting from SPI, then the BIOS Boot-Block size soft strap determines if A16, A17,

or A18 should be inverted if Top Swap is enabled.

If PCH is strapped for Top Swap (GNT3#/GPIO55 is low at rising edge of PWROK),

then this bit cannot be cleared by software. The strap jumper should be removed and

the system rebooted.

Signal

Usage

When

Sampled

Comment

GNT3# /

GPIO55

Top-Block

Swap

Override

Rising edge

of PWROK

The signal has a weak internal pull-up. If the signal is sampled low,

this indicates that the system is strapped to the “top-block swap”

mode.

The status of this strap is readable using the Top Swap bit (Chipset

Config Registers: Offset 3414h:Bit 0).

NOTES:

The internal pull-up is disabled after PLTRST# deasserts.

Software will not be able to clear the Top Swap bit until the

system is rebooted without GNT3#/GPIO55 being pulled

down.

C200 Datasheet(PDF) 55 Page - Intel Corporation

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