C200 datasheet(46/82 Pages) INTEL

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Documentation Changes

Specification Update

SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5)

Address Offset: 48h

Attribute:

R/W

Default Value:

00h

Size:

8 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5)

Address Offset: 4Ah–4Bh

Attribute:

R/W

Default Value:

0000h

Size:

16 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5)

Address Offset: 54h–57h

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

Bit

Description

7:4

Reserved

3:0

SDMA_CNT Field 1 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Bit

Description

15:10

Reserved

9:8

SDMA_TIM Field 2— R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

7:2

Reserved

1:0

SDMA_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Bit

Description

31:24 Reserved

23:16

IDE_CONFIG Field 6 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Reserved

IDE_CONFIG Field 5 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Reserved

IDE_CONFIG Field 4 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

11:8

Reserved

7:4

IDE_CONFIG Field 3 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Reserved

C200 Datasheet(PDF) 46 Page - Intel Corporation

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