C200 datasheet(29/82 Pages) INTEL

29 / 82 page

Specification Update

Specification Clarifications

c. the following is added to the list of items describing when Intel Rapid Storage

Technology is not available in section 5.16.7:

2. The SATA controller is programmed in RAID mode, but the AIE bit (D31:F2:Offset

9Ch bit 7) is set to 1.

d. The SATA D31:F2 Device ID table is updated; see PCH Device and Revision

Identification section in this document.

SATA Hot Plug Operation

Section 5.16.5 Hot Plug Operation is modified as shown below. Section 5.16.5.1 is

removed.

The PCH supports Hot Plug Surprise removal and Insertion Notification. An internal

SATA port with a Mechanical Presence Switch can support PARTIAL and SLUMBER with

Hot Plug Enabled. Software can take advantage of power savings in the low power

states while enabling hot plug operation. Refer to chapter 7 of the AHCI specification

for details.

GPIO13 Voltage Tolerance

GPIO13 is powered by VccSusHDA well and therefore, the voltage tolerance value

varies according to the voltage connected to VccSusHDA. The following clarifications

are made:

a. Table 2-24, GPIO13 Tolerance is change from “3.3 V” to “3.3 V or 1.5 V” and the

following note is added to table 2-24: “GPIO13 is powered by VccSusHDA (either 3.3 V

or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA.”

b. The following note is added to GPIO13 in table 3-2 as note 16: “GPIO13 is powered

by VccSusHDA (either 3.3 V or 1.5 V). Pin tolerance is determined by VccSusHDA

voltage.”

c. The following note is added to HDA_DOCK_RST#/GPIO13 in table 3-3 as note 24:

“HDA_DOCK_RST#/GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Pin

tolerance is determined by VccSusHDA voltage.”

EHCI Configuration Programming

a. Section 16.1.31 EHCIIR1—EHCI Initialization Register 1 bits 18 and 10:9 are

changed as shown:

b. Section 16.1.32 EHCIIR2—EHCI Initialization Register 2 is modified as shown:

Bit

Description

EHCI Initialization Register 1 Field 2— R/W. BIOS may write to this bit field.

10:9

EHCI Initialization Register 1 Field 1— R/W. BIOS may write to this bit field.

Bit

Description

31:30 Reserved

EHCI Initialization Register 2 Field 6 — R/W. BIOS may write to this bit field.

28:20 Reserved

EHCI Initialization Register 2 Field 5 — R/W. BIOS may write to this bit field.

18:12 Reserved

C200 Datasheet(PDF) 29 Page - Intel Corporation

C200 Datasheet(HTML) 29 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL