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C200 Datasheet(PDF) 32 Page - Intel Corporation

Part # C200
Description  Intel® 6 Series Chipset and Intel® C200 Series Chipset
PDF  82 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

C200 Datasheet(HTML) 32 Page - Intel Corporation

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Specification Clarifications
32
Specification Update
d. The following section is added after section 5.13.10.6.
SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior
The following tables summarize SUSPWRDNACK/SUSWARN#/GPIO30 pin behavior.
NOTES:
1.
Intel ME will drive SPDA pin high if power package 1 or DC. Intel ME will drive SPDA pin
low if power package 2.
2.
If entering Deep S4/S5, pin will assert and become undriven ("Off") when suspend well
drops upon Deep S4/S5 entry.
e. The following note is added to Figure 8-1 G3 w/RTC Loss to S4/S5 (With Deep S4/S5
Support) Timing Diagram:
VccSus rail ramps up later in comparison to VccDSW due to assumption that SLP_SUS#
is used to control power to VccSus.
SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior
Deep
S4/S5
(Supported
/Not-Supp
orted)
GPIO30
Input/Out
put
(Determine
by
GP_IO_SEL
bit)
Pin Value in
S0
Pin Value in
Sx/Moff
Pin Value
in Sx/M3
Pin Value
in Deep
S4/S5
SUSPWRDNACK
Not
Supported
Native
Depends on
Intel® ME
power
package and
power source
(Note 1)
Depends on
Intel ME
power
package and
power source
(Note 1)
Intel ME
drives low
Off
SUSWARN#
Supported
Native
1
1 (Note 2)
1
Off
GPIO30
Don't Care
IN
High-Z
High-Z
High-Z
Off
Don't Care
OUT
Depends on
GPIO30
output data
value
Depends on
GPIO30
output data
value
Depends
on GPIO30
output
data value
Off
SUSPWRDNACK during reset
Reset Type
Reset Initiated By
SPDA Value
Power Cycle Reset
Host or Intel ME
(Power Cycle Reset)
Intel ME drives low
Global Reset
Host
(using CF9GR)
Host drives low
(using BIOS flow)
Intel ME
Intel ME drives low
HW/WDT expiration
Steady-state value



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