C200 datasheet(77/82 Pages) INTEL

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Specification Update

Documentation Changes

NOTE: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using processor message

interrupts.

Mapping Option #2 (Standard Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its

own routing control. The interrupts can be routed to various interrupts in the 8259 or

I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a

timer is set for edge-triggered mode, the timers should not be shared with any PCI

interrupts.

For the PCH, the only supported interrupt values are as follows:

Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only).

Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only).

Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only).

Interrupts from Timer 4, 5, 6, 7 can only be delivered using processor message

interrupts.

Mapping Option #3 (Processor Message Option)

In this case, the interrupts are mapped directly to processor messages without going to

the 8259 or I/O (x) APIC. To use this mode, the interrupt must be configured to

edge-triggered mode. The Tn_PROCMSG_EN_CNF bit must be set to enable this mode.

When the interrupt is delivered to the processor, the message is delivered to the

address indicated in the Tn_PROCMSG_INT_ADDR field. The data value for the write

cycle is specified in the Tn_PROCMSG_INT_VAL field.

Notes:

1. The processor message interrupt delivery option has HIGHER priority and is

mutually exclusive to the standard interrupt delivery option. Thus, if the

Tn_PROCMSG_EN_CNF bit is set, the interrupts will be delivered directly to the

processor rather than via the APIC or 8259.

Table 5-41 Legacy Replacement Routing

Timer

8259 Mapping

APIC Mapping

Comment

0IRQ0

IRQ2

In this case, the 8254 timer will

not cause any interrupts

1IRQ8

IRQ8

In this case, the RTC will not cause

any interrupts.

2 & 3

Per IRQ Routing

Field.

Per IRQ Routing Field

4, 5, 6, 7

not available

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