C200 datasheet(49/82 Pages) INTEL

49 / 82 page

Specification Update

Documentation Changes

12.2.3 GBECSR3—Gigabit Ethernet Capabilities and Status Register 3

Address Offset: MBARA + 20h

Attribute:

R/W

Default Value:

1000XXXXh

Size:

32 bit

12.2.4 GBECSR4—Gigabit Ethernet Capabilities and Status Register 4

Address Offset: MBARA + 2Ch

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

12.2.5 GBECSR5—Gigabit Ethernet Capabilities and Status Register 5

Address Offset: MBARA + F00h

Attribute:

R/W

Default Value:

00010008h

Size:

32 bits

Bit

Description

31:29 Reserved

Ready Bit (RB) — R/W.

Set to 1 by the Gigabit Ethernet Controller at the end of the MDI transaction. This bit

should be reset to 0 by software at the same time the command is written.

27:26

MDI Type — R/W.

01 = MDI Write

10 = MDI Read

All other values are reserved.

25:21 LAN Connected Device Address (PHYADD) — R/W.

20:16 LAN Connected Device Register Address (PHYREGADD) — R/W.

15:0

DATA — R/W.

Bit

Description

WOL Indication Valid (WIV) — R/W.

Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is

valid.

WOL Enable Setting by BIOS (WESB) — R/W.

1 = WOL Enabled in BIOS.

0 = WOL Disabled in BIOS.

29:0

Reserved

Bit

Description

31:6

Reserved

SW Semaphore FLAG (SWFLAG) — R/W.

This bit is set by the device driver to gain access permission to shared CSR registers

with the firmware and hardware.

4:0

Reserved

C200 Datasheet(PDF) 49 Page - Intel Corporation

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