C200 datasheet(45/82 Pages) INTEL

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Specification Update

Documentation Changes

IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2)

Address Offset: 54h–57h

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

d. Section 15.1.21 IDE_TIM — IDE Timing Register is modified as shown:

e. The following paragraph is added to the register summary of section 15.1.21

IDE_TIM — IDE Timing Register:

Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These

bits have no effect on hardware.

f. The following registers are added immediately following section 15.1.21:

9:8

SDMA_TIM Field 3— R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

7:6

Reserved

5:4

SDMA_TIM Field 2— R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

3:2

Reserved

1:0

SDMA_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Bit

Description

Bit

Description

31:24 Reserved

23:12

IDE_CONFIG Field 2 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

11:8

Reserved

7:0

IDE_CONFIG Field 1 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Bit

Description

IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or

Secondary decode.

0 = Disable.

1 = Enables the PCH to decode the associated Command Block and Control Block.

14:12

IDE_TIM Field 2 — R/W. This field is R/W to maintain software compatibility. This field

has no effect on hardware.

11:10 Reserved

9:0

IDE_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field

has no effect on hardware.

C200 Datasheet(PDF) 45 Page - Intel Corporation

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