C200 datasheet(48/82 Pages) INTEL

48 / 82 page

Documentation Changes

Specification Update

12.2.1 GBECSR1—Gigabit Ethernet Capabilities and Status Register 1

Address Offset: MBARA + 00h

Attribute:

R/W

Default Value:

00100241h

Size:

32 bit

12.2.2 GBECSR2—Gigabit Ethernet Capabilities and Status Register 2

Address Offset: MBARA + 18h

Attribute:

R/W/SN

Default Value:

01501000h

Size:

32 bit

F00h-F03

GBECSR5

Gigabit Ethernet Capabilities and

Status Register 5

00010008h

R/W

F10h-F13

GBECSR6

Gigabit Ethernet Capabilities and

Status Register 6

0004000Ch

R/W/SN

5400h-54

03h

GBECSR7

Gigabit Ethernet Capabilities and

Status Register 7

XXXXXXXXh

R/W

5404h-54

07h

GBECSR8

Gigabit Ethernet Capabilities and

Status Register 8

XXXXXXXXh

R/W

5800h-58

03h

GBECSR9

Gigabit Ethernet Capabilities and

Status Register 9

00000008h

R/W/SN

Table 12-2. Gigabit LAN Capabilities and Status Registers Address Map

(Gigabit LAN —MBARA) (Sheet 2 of 2)

MBARA

+ Offset

Mnemonic

Default

Attribute

Bit

Description

31:25 Reserved

PHY Power Down (PHYPDN) — R/W.

When cleared (0b), the PHY power down setting is controlled by the internal logic of

PCH.

23:0

Reserved

Bit

Description

31:21 Reserved

PHY Power Down Enable (PHYPDEN) — R/W/SN.

When set, this bit enables the PHY to enter a low-power state when the LAN controller

is at the DMoff/D3 or with no WOL.

19:0

Reserved

C200 Datasheet(PDF) 48 Page - Intel Corporation

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