IP100A LF
Preliminary Data Sheet
16/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
7
Operation
7.1
Initialization
The IP100A LF provides several resets. The assertion of the hardware reset signal on the PCI bus
causes a complete reset of the IP100A LF. A similar reset is available via software using the GlobalReset
bit of the AsicCtrl register. The AsicCtrl register also allows for selective reset of particular functional
blocks of the IP100A LF. See the Registers and Data Structures section for details on using the AsicCtrl
register for resetting the IP100A LF.
Shortly after reset, the IP100A LF will read the contents of an external EEPROM, placing the data read
into the following registers:
• ConfigParm
• AsicCtrl (least significant 16 bits)
• SubsystemVendorId
• SubsystemId
• StationAddress
• Data
There are several other registers which must be configured by the host during initialization. These registers
include the IP100A LF PCI configuration registers which are set during a Power On Self Test (POST)
routine performed by the host system. Specifically, the registers set during this stage of initialization are:
• ConfigCommand enables adapter operation by allowing it to respond to and generate PCI bus cycles.
ConfigCommand is also used to enable parity error generation.
• loBaseAddress sets the I/O base address for the IP100A LF registers.
• MemBaseAddress sets the memory base address for the IP100A LF registers.
• ExpRomBaseAddress sets the base address and size for an installed expansion ROM, if any.
• CacheLineSize indicates the system’s cache line size. This value is used by the IP100A LF to
optimize bus master data transfers.
• LatencyTimer sets the length of time the IP100A LF can hold the PCI bus as a bus master.
• InterruptLine maps IP100A LF’s interrupt request to a specific interrupt line (level) on the system
board.
• AsicCtrl is used to setup internal operations and parameters.
The IP100A LF can be accessed across the PCI bus without setting the PCI registers or loading data
from an external EEPROM. In this Forced Configuration mode (useful for embedded applications without
an EEPROM), the IP100A LF is configured as follows:
• I/O base address 0x200
• I/O target cycles enabled
• Memory target cycles disabled
• Bus master cycles enabled
7.2
Register Programming
After initialization, an additional set of registers specific to operation of the Ethernet network must be
programmed.
The first setting relates to the Auto-Negotiation function. The IP100A LF PHY layer performs the
Auto-Negotiation process, and the host system must communicate with the PHY to determine the link
status. Once the result of Auto-Negotiation is determined, if a full duplex mode has been chosen, the
host system must set the FullDuplexEnable bit in the MACCtrl0 register. Other modes chosen during
Auto-Negotiation do not require any IP100A LF register settings.
The ReceiveMode register determines which types of frames, based on address matching mechanism,
the IP100A LF will receive. The end station address is loaded from the EEPROM, or the host system can
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