IP100A LF
Preliminary Data Sheet
82/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.12 InterruptLine
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3c
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
InterruptLine
R/W
Interrupt Line. InterruptLine specifies the interrupt level used by the
IP100A LF. By setting InterruptLine the host system may configure
the appropriate interrupt vector for its Interrupt Service Routine.
For 80x86 processor based host systems, InterruptLine
corresponds to the IRQ number (0x00 through 0x0F), with the
value 0xFF corresponding to disabled interrupts.
11.6.13 InterruptPin
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3d
Default .......................... 0x01
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
InterruptPin
R
Interrupt Pin. InterruptPin indicates which PCI interrupt signal the
IP100A LF will utilize. The IP100A LF always utilizes the INTAN
interrupt signal, corresponding to an InterruptPin value of 0x01.
11.6.14 IoBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x10
Default .......................... 0x00000001
Width ............................ 32 bits
IoBaseAddress is used to define the I/O base address for the IP100A LF. PCI systems requires that the
I/O base address be set as if the system used 32-bit I/O addressing. The upper 25 bits of IoBaseAddress
are read/write accessible, indicating that the IP100A LF requires 128 bytes of I/O space in the system I/O
map.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
IoBaseAddrInd
R
I/O Base Address Indicator. When IoBaseAddrInd is a logic 1,
IoBaseAddress contains the valid I/O base address for the IP100A
LF.
6..1
Reserved
N/A
Reserved for future use.
31..7
IoBaseAddress
R/W
I/O Base Address. IoBaseAddress contains the 25 bit I/O base
address value. The IP100A LF uses 128 bytes of I/O address
space.
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