IP100A LF
Preliminary Data Sheet
84/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
2..1
MemMapType
R
Memory Map Type. MemMapType defines how the host system
maps the IP100A LF’s registers within the host system memory
space. Bit 2 of MemMapType is always a logic 0, while bit 1 is
loaded from the Lower1Meg bit of the ConfigParm field within an
EEPROM during auto initialization of the IP100A LF.
BIT 2
BIT 1
REGISTER MAPPING
0
0
Anywhere within a 32 bit address space
0
1
Lower 1 megabyte of 32 bit address space
1
x
Undefined
6..3
Reserved
N/A
Reserved for future use.
31..7
MemBaseAddress
R/W
Memory Base Address. MemBaseAddress contains the 25 bit
memory base address value. The IP100A LF uses 128 bytes of
I/O space.
11.6.18 MinGnt
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3e
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
MinGnt
R
Minimum Grant Time. MinGnt specifies, in 250 ns increments,
how long a burst period the IP100A LF requires when operating
as a bus master. Bits 7 through 4 of the MinGnt value are loaded
from the ConfigParm field within an EEPROM during auto
initialization of the IP100A LF.
11.6.19 NextItemPtr
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x51
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
NextItemPtr
R
Next Item Pointer. NextItemPtr indicates the next capability data
structure in the capabilities list. When NextItemPtr is set to the
value 0x00, there are no further data structures.
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