94 / 97 page
IP100A LF
Preliminary Data Sheet
94/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
12.3
AC Characteristics
PARAMETER
SYMBOL
PARAMETER
DESCRIPTION
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
PCI INTERFACE
Trc
RSTN cycle
300
ns
Trr
Rising edge or RSTN to chip recovery
1
µs
Tcc
PCICLK cycle
30
ns
Tch
PCICLK high
11
ns
Tcl
PCICLK low
11
ns
Trv
PCICLK rise to bused signal valid
2
11
ns
Trvp
PCICLK rise to REQN, GNTN valid
2
12
ns
Trzo
PCICLK rise to signal on
2
ns
Troz
PCICLK rise to signal off
28
ns
Tsu
bused signal setup wrt PCICLK rise
7
ns
Tsup1
GNTN setup wrt PCICLK rise
10
ns
Tsup2
REQN setup wrt PCICLK rise
12
ns
Thd
signal hold wrt PCICLK rise
0
ns
Trstoff
RSTN low to output signal float
40
ns
EEPROM INTERFACE
Tskc
EESK cycle
1us
-
ns
Tskh
EESK high
250
-
ns
Tskl
EESK low
250
-
ns
Tcs
EECS low
250
-
ns
Tpd
EEDI valid wrt EESK rise
100
-
ns
Tcsk
EECS setup wrt EESK rise
50
-
ns
Tcsh
EECS hold wrt EESK fall
0
-
ns
Tdos
EEDO setup wrt EESK rise
70
500
ns
Tdoh
EEDO hold wrt EESK rise
-
500
ns
100BASE-TX MDI
TR /TF
Rise/Fall Time
3
5
ns
TIMB
Rise/Fall Time Imbalance
0
500
ps
TDCD
Duty Cycle Distortion
0.5
ns
TJ
Maximum output jitter (peak to peak)
0.7
1.4
ns
10BASE-T MDI
TR10 /TF10
Rise/Fall Time
25
ns
TJ10
Transmit Jitter
3.5
ns
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