IP100A LF
Preliminary Data Sheet
89/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
BIT DESCRIPTION
4
ExpRomDisable
Expansion
ROM
Disable.
ExpRomDisable
corresponds
to
the
ExpRomDisable bit in the AsicCtrl register.
5
PhySpeed10
Physical Layer Device Speed 10Mbps. PhySpeed10 corresponds to the
PhySpeed10 bit in the AsicCtrl register.
6
PhySpeed100
Physical Layer Device Speed 100Mbps. PhySpeed100 corresponds to
the PhySpeed100 bit in the AsicCtrl register.
7
PhyMedia
Physical Layer Device Media. PhyMedia corresponds to the PhyMedia bit
in the AsicCtrl register.
14..8
Reserved
Reserved for future use.
15
WakeOnLanEnable Wake On LAN Enable. WakeOnLanEnable corresponds to the
WakeOnLanEnable bit in the WakeEvent register.
11.7.2 ConfigParm
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x00
Access Mode ................ Read Only
Width ............................ 16 bits
BIT
BIT NAME
BIT DESCRIPTION
0
FastBackToBack
Fast
Back
to
Back.
FastBackToBack
corresponds
to
the
FastBackToBack bit in the ConfigStatus register.
1
Lower1Meg
Lower 1 Megabyte. Lower1Meg corresponds to bit 1 of the MemMapType
bit in the MemBaseAddress register.
2
DisableMemBase
Disable Memory Base Address Register. DisableMemBase does not
correspond directly to any register accessible by the host system. If
DisableMemBase is a logic 1 during auto initialization of the IP100A LF,
the MemBaseAddress register will be disabled. When disabled, the value
returned when the MemBaseAddress register is read is undefined.
3
D3ColdPme
D3 Cold Power Management Event. D3ColdPme corresponds to the
PmeSupport bit in the PowerMgmtCap register.
4
D1Support
D1 Power State Support. D1Support corresponds to the D1Support bit in
the PowerMgmtCap register.
5
D2Support
D2 Power State Support. D2Support corresponds to the D2Support bit in
the PowerMgmtCap register.
6
PmeEn
Power Management Event Enable. PmeEn corresponds to the PmeEn bit
in the PowerMgmtCtrl register.
10..7
MinGnt
Minimum Grant. MinGnt corresponds to bits 7 through 4 of the MinGnt
register.
15..11
MaxLat
Maximum Latency. MaxLat corresponds to bits 5 through 1 of the MaxLat
register.
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