IP100A LF
Preliminary Data Sheet
79/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.7 ConfigStatus
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x06
Default .......................... 0x0210
Width ............................ 16 bits
ConfigStatus is used to record status information for PCI bus events. Read/write bits inConfigStatus can
only be reset, not set, by writing to this register. Bits are reset by writing a one to the corresponding bit.
BIT
BIT NAME
R/W
BIT DESCRIPTION
3..0
Reserved
N/A
Reserved for future use.
4
Capabilities
R
Capabilities. Capabilities is a logic 1 to indicate a set of extended
capabilities registers exists for the IP100A LF. The CapPtr
register indicates the first address location of the extended
capabilities register set.
6..5
Reserved
N/A
Reserved for future use.
7
FastBackToBack
R
Fast Back to Back. When FastBackToBack is a logic 1 the
IP100A LF when operating as a Target, supports fast
back-to-back transactions as defined by the criteria in the section
3.4.2 of the PCI specification.
8
DataParityReported R/W
Master Data Parity Error. When DataParityReported is a logic 1,
the IP100A LF when operating as a Master, has detected the
PERRN signal asserted, and the ParityErrorResponse bit in the
ConfigCommand register as a logic 1.
10..9
DevselTiming
R
Device Select Timing. DevselTiming is used to encode the
slowest time with which the IP100A LF asserts the DEVSELN
signal. A value of 0x1 for DevselTiming indicates support for
“medium” speed DEVSELN assertion.
11
SignaledTargetAbort R/W
Signaled Target Abort. The IP100A LF sets SignaledTargetAbort
to a logic 1 when the IP100A LF terminates a bus transaction with
target-abort.
12
ReceivedTargetAbort R/W
Received
Target
Abort.
The
IP100A
LF
sets
ReceivedTargetAbort to a logic 1 when, operating as a bus
master, a IP100A LF bus transaction is terminated with
target-abort.
13
ReceivedMasterAbort R/W
Received
Master
Abort.
The
IP100A
LF
sets
ReceivedMasterAbort to a logic 1 when, operating as a bus
master, a IP100A LF bus transaction is terminated with
master-abort.
14
SignaledSystemError R/W
Signaled System Error. When SignaledSystemError is a logic 1,
the IP100A LF asserts the SERRN signal.
15
DetectedParityError R/W
Detected Parity Error. When DetectedParityError is a logic 1 the
IP100A LF has detected a parity error, regardless of whether
parity error handling is enabled.
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