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IP100ALF Datasheet(PDF) 47 Page - List of Unclassifed Manufacturers

Part # IP100ALF
Description  Integrated 10/100 Ethernet MAC PHY
PDF  97 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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IP100ALF Datasheet(HTML) 47 Page - List of Unclassifed Manufacturers

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IP100A LF
Preliminary Data Sheet
47/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
24
Reserved
N/A
Reserved for future use.
25
InterruptRequest
W
Interrupt Request. When InterruptRequest is a logic 1, the
IntRequested bit of the IntStatus register is set to a logic 1.
InterruptRequest is self-clearing.
26
ResetBusy
R/W
Reset Busy. When ResetBusy is a logic 1 a reset process is in
progress. After asserting a reset using the GlobalReset, RxReset,
or TxReset bits, the ResetBusy bit must be polled (or periodically
read) until it is a logic 0 indicating the reset operation is complete.
31..27
Reserved
N/A
Reserved for future use.



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