IP100A LF
Preliminary Data Sheet
27/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
can only take place in the D1, D2, or D3 states, and MagicPktEnable has no effect when the IP100A LF
is in the D0 power state. The Magic Packet must also pass the address matching criteria set in
ReceiveMode. A Magic Packet may also be a broadcast frame. When the IP100A LF detects a Magic
Packet, it signals a wake event on PMEN (if PMEN assertion is enabled), and sets the MagicPktEvent bit
in WakeEvent.
The IP100A LF can also signal a wake event when it senses a change in the network link state, either
from LINK_OK to LINK_FAIL, or vice versa. Link state wake is controlled by the LinkEventEnable bit in
the WakeEvent register. At the time LinkEventEnable is set by the host system, the IP100A LF samples
the current link state. It then waits for the link state to change. If the link state changes before the IP100A
LF returns to state D0 or LinkEventEnable is cleared, LinkEvent is set in WakeEvent, and (if it is enabled)
the PMEN signal is asserted.
10.1
Wake Event
When a desired wake event occurs, the IP100A LF sets the appropriate event bit in the WakeEvent
register, sets the PmeStatus bit in the PowerMgmtCtrl register, and asserts the PMEN signal.
The host system responds to PMEN by scanning the power management configuration registers of all
devices, looking for the device which asserted PMEN. If the device with the IP100A LF signaled wake,
the system will find PmeStatus set in IP100A LF’s PowerMgmtCtrl register. The operating system then
clears the PmeEn bit in the PowerMgmtCtrl register causing PMEN to be de-asserted.
The operating system raises the power state (probably to D0) by writing to the PowerState bits in the
PowerMgmtCtrl register. If the IP100A LF was previously in the D3 state, PCI configuration is lost and
must be restored by the operating system.
The host system must set TxReset to clear any wake patterns out of the transmit FIFO (if this is not done,
the patterns will be treated as frames and transmitted once the transmitter is enabled).
The host system reads the WakeEvent register to determine the wake event, and if requested, passes it
back to the operating system. The host system restores any volatile state that was saved in the power
down sequence. The host system re-enables interrupts by programming IntEnable. The host system
restores the RxDMAList (and any other data structures required for operation). Any wake packets in the
receive FIFO are transferred by receive DMA and passed to the operating system.
10.2
Power Down
D0u and D0i are mutually exclusive. The moment that the IoBaseAddress register or the
MemBaseAddress is written by the host, then IP100A LF enters D0u. When D0u is active, the PHY is
completely powered down and all clocks (AsicClk, TxClk, RxClk) are gated off except PciClk. The
IP100A LF consumes less than 70 mA in D0u. Make sure that the LED drivers are off. When IP100A LF
is in D0i, the PHY is powered up and ready to transmit and receive packets. In Forced Config mode
(motherboard applications), IP100A LF is always in D0i mode. Another way to indicate D0u is to check
the non-zero value in the programmable field of IoBaseAddress or MemBaseAddress. In WOL the PHY
should be fully functional to receive Magic Packets. In WOL mode, D0u should be forced to low before
passing to the PHY.
When in the D3 state, if PMEN is de-asserted on the PCI bus the IP100A LF will enter Power Down.
When in Power Down mode, the PHY is completely powered down. All clocks (AsicClk, TxClk, RxClk)
except PciClk are gated off. When the PCI bus is powered down, the IP100A LF consumes less than 5
mA.
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