IP100A LF
Preliminary Data Sheet
54/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
6
IntRequested
R/W
Interrupt Requested Interrupt. IntRequested is a logic 1 after the
host system requests an interrupt by setting InterruptRequest bit
of the AsicCtrl register.
7
UpdateStats
R/W
Update Statistics Interrupt. UpdateStats is a logic 1 to indicate
that one or more of the statistics registers is nearing an overflow
condition (typically half of its maximum value). The host system
should respond to an UpdateStats interrupt by reading all of the
statistic
registers,
thereby
acknowledging
and
clearing
UpdateStats bit.
8
LinkEvent
R/W
Link Event Interrupt. LinkEvent is a logic 1 to indicate a change in
the state of the Ethernet link.
9
TxDMAComplete
R/W
Transmit DMA Complete Interrupt. TxDMAComplete is a logic 1
to indicate that a transmit DMA operation has completed, and the
frame’s corresponding TFD had the TxDMAComplete bit in the
TxFrameControl field set to a logic 1.
10
RxDMAComplete
R/W
Receive DMA Complete Interrupt. RxDMAComplete is a logic 1 to
indicate that a frame receive DMA operation has completed.
11
Reserved
N/A
Reserved for future use.
15..12
Reserved
N/A
Reserved for future use.
11.4.9 IntStatusAck
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x4a
Default .......................... 0x0000
Width ............................ 16 bits
IntStatusAck is another version of the IntStatus register, having the same bit definition as IntStatus, but
providing additional functionality to reduce the number of I/O operations required to perform common
tasks related to interrupt handling. In addition to returning the IntStatus value, when read IntStatusAck
also acknowledges the TxDMAComplete, RxDMAComplete, IntRequested, MACControlFrame, and
LinkEvent interrupt bits within the IntStatus register (if they are set), and clears the IntEnable register
(preventing subsequent events from generating an interrupt).
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
InterruptStatus
R
See InterruptStatus in the IntStatus register.
1
HostError
R
See HostError in the IntStatus register.
2
TxComplete
R
See TxComplete in the IntStatus register.
3
MACControlFrame
R
See MACControlFrame in the IntStatus register.
4
RxComplete
R
See RxComplete in the IntStatus register.
5
Reserved
R
Reserved for future use.
6
IntRequested
R
See IntRequested in the IntStatus register.
7
UpdateStats
R
See UpdateStats in the IntStatus register.
8
LinkEvent
R
See LinkEvent in the IntStatus register.
9
TxDMAComplete
R
See TxDMAComplete in the IntStatus register.
10
RxDMAComplete
R
See RxDMAComplete in the IntStatus register.
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