IP100A LF
Preliminary Data Sheet
22/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
In some host systems, it may be desirable to copy received frame data out of the scatter buffer to the
protocol buffer while the frame is still being transferred by RxDMA. The RxDMAStatus register is
provided for this purpose. If the host system sets the RxDMAHalt bit in the DMACtrl register, reads the
RxDMAListPtr register and the RxDMAStatus register, then sets the RxDMAResume bit in the DMACtrl
register, the host system can determine how much of the frame has been transferred by RxDMA. The
RxDMAStatus register indicates the number of bytes transferred by RxDMA for the current RFD pointed
to by the RxDMAListPtr register. The host system can then perform memory copies out of the RFD buffer
concurrently with the RxDMA operation.
7.5
Interrupts
The term “interrupt” is used loosely to refer to interrupts and indications. An interrupt is the actual assertion
of the hardware interrupt signal on the PCI bus. An indication, or a set bit in the IntStatus register, is the
reporting of any event enabled by the host. The host system will configure the IP100A LF to generate an
interrupt for any indication that is of interest to it. There are 10 different types of interrupt indications that
can be generated by the IP100A LF. The IntEnable register controls which of the 10 indication bits can
assert a hardware interrupt. In order for an indication bit to be allowed to generate an interrupt, its
corresponding bit-position in IntEnable must be set. When responding to an interrupt, the host reads the
IntStatus register to determine the cause of the interrupt. The least significant bit of IntStatus,
InterruptStatus, is always set whenever any of the interrupts are asserted. InterruptStatus must be explicitly
acknowledged (cleared) by writing a 1 into the bit in order to prevent spurious interrupts on the host bus.
Interrupts are acknowledged by the host carrying out various actions specific to each interrupt.
8
Statistics
The IP100A LF implements 16 statistics counters of various widths. Each statistic implemented complies
to the corresponding definition given in the IEEE 802.3 standard. Setting the StatisticsEnable bit in the
MACCtrl1 register enables the gathering of statistics. Reading a statistics register will clear the read
register. Statistic registers may be read without disabling statistics gathering. For diagnostics and testing
purposes, the host system may write a value to a statistic register, in which case the value written is
added to the current value of the register. Whenever one or more of the statistics registers reaches 75%
of its maximum value, an UpdateStats interrupt is generated. Reading that statistics register will
acknowledge the UpdateStats interrupt. A summary of the transmit and receive statistics follows.
Detailed descriptions of the statistic registers related to data transmission and reception can be found in
the Registers and Data Structures section.
8.1
Transmit Statistics
• FramesTransmittedOk: The number frames of all types transmitted without errors. Loss of carrier is
not considered to be an error by this statistic.
• BroadcastFramesTransmittedOk: The number of frames with broadcast destination address that are
transmitted without errors.
• MulticastFramesTransmittedOk: The number of frames with multicast destination address that are
transmitted without errors.
• OctetsTransmittedOk: The number of total octets for all frames transmitted without error.
• FramesWithDeferredXmission: A count of frames whose transmission was delayed on it’s first
attempt because network traffic.
• FramesWithExcessiveDeferral: If the transmission of a frame has been deferred for an excessive
period of time due to network traffic, the event is recorded in this statistic.
• SingleCollisionFrames: Frames that are transmitted without errors after one and only one collision
(including late collisions) are counted by this register.
• MultipleCollisionFrames: All frames transmitted without error after experiencing from 2 through 15
collisions (including late collisions) are counted here.
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