IP100A LF
Preliminary Data Sheet
45/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
been received.
1 and 0 indicates the
data receiving is in
progress.
LED_DPLXN Logic 0 means the link is
established based on
FULL Duplex Mode,
while logic 1 indicates
HALF Duplex Mode.
Alternating logic 1 and 0
indicates COLLISION
has occurred.
Logic 0 means the link
is established based on
FULL Duplex Mode,
while logic 1 indicates
HALF Duplex Mode.
2
TxLargeEnable
R/W
Transmit Large Frames Enable. If TxLargeEnable is a logic 1, the
IP100A LF may transmit frames which are larger in size than the
IP100A LF transmit FIFO.
3
RxLargeEnable
R/W
Receive Large Frames Enable. If RxLargeEnable is a logic 1, the
IP100A LF may receive frames which are larger than the IP100A
LF receive FIFO.
4
ExpRomDisable
R/W
Expansion ROM Disable. If ExpRomDisable is a logic 1,
accesses to the on-adapter Expansion ROM are disabled and
read to the Expansion ROM return 0x00000000 while writes to
the Expansion ROM are ignored.
5
PhySpeed10
R
Physical Device 10Mbps Capable. If PhySpeed10 is a logic 1, the
IP100A LF PHY is capable of operating at 10Mbps.
6
PhySpeed100
R
Physical Device 100Mbps Capable. If PhySpeed100 is a logic 1,
the IP100A LF PHY is capable of operating at 100Mbps.
7
PhyMedia
R
Physical Device Media Type. If PhyMedia is a logic 0, copper
media is in use. If PhyMedia is a logic 1, fiber media is in use. The
combination of PhyMedia, PhySpeed100, and PhySpeed10
defines the capabilities of the PHY.
PHY
MEDIA
PHY
SPEED100
PHY
SPEED10
PHY CAPABILITY
0
0
0
Undefined
0
0
1
10BASE-T
0
1
0
100BASE-T
0
1
1
100BASE-T or 10BASE-T
1
0
0
Undefined
1
0
1
10BASE-F
1
1
0
100BASE-F
1
1
1
100BASE-F or 10BASE-F
9..8
ForcedConfig[1..0]
R/W
Forced Configuration. ForcedConfig[1..0] is used to enable and
select a Forced Configuration mode for the IP100A LF. Forced
Configuration mode is targeted toward embedded applications
which do not utilize an EEPROM. In Forced Configuration mode,
the IP100A LF is accessed via a PCI bus without first performing
PCI configuration or loading parameters from an EEPROM.
The ForcedConfig[1..0] bits 9 through 8 can also be set on reset
using ED[4:3].
BIT 9
BIT 8
FORCED CONFIGURATION MODE
0
0
None
0
1
1
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