IP100A LF
Preliminary Data Sheet
86/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.21 PowerMgmtCtrl
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x54
Default Value ................ 0x4000
Width ............................ 16 bits
PowerMgmtCtrl allows control over the power state and the power management interrupts.
BIT
BIT NAME
R/W
BIT DESCRIPTION
1..0
PowerState
R/W
Power State. PowerState indicates the current power state of the
IP100A LF. If PowerState is set to a value other than 0x0, the
IP100A LF will not respond to PCI I/O or memory cycles, nor will
the IP100A LF be able to generate PCI bus master cycles.
BIT 1
BIT 0
POWER STATE
0
0
D0
0
1
D1
1
0
D2
1
1
D3
7..2
Reserved
N/A
Reserved for future use.
8
PmeEn
R/W
Power Management Event Enable. When PmeEn is a logic 1, the
IP100A LF is allowed to report wake events on the PMEN signal.
The criteria for generating wake events is defined by the
WakeEvent register. PmeEn is loaded from the ConfigParm field
of an EEPROM during auto initialization of the IP100A LF.
12..9
DataSelect
R/W
Data Select. DataSelect is used to select which data is to be
reported through the Data register and DataScale field.
14..13
DataScale
R
Data Scale. DataScale indicates the scaling factor to be used
when interpreting the value of the Data register. The
interpretation of the scale values is defined as follows:
DATASCALE
SCALE FACTOR
0x0
Unknown
0x1
0.1
0x2
0.01
0x3
0.001
15
PmeStatus
R/W
Power Management Event Status. When PmeStatus is a logic 1 a
wake event has occurred. PmeStatus may be a logic 1 regardless
of the value of PmeEn. Writing a logic 1 to PmeStatus will set
PmeStatus to a logic 0. Writing a logic 0 to PmeStatus has no
effect.
11.6.22 RevisionId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x08
Default .......................... Depends on revision of actual device. See description below.
Width ............................ 8 bits
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
