IP100A LF
Preliminary Data Sheet
62/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.20 StationAddress
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x54, 0x56, 0x58
Default .......................... 0x000000000000
Width ............................ 48 bits (accessible as 3, 16 bit words)
StationAddress is used to define the individual destination address that the IP100A LF will respond to
when receiving frames. Network addresses are generally specified in the form of 01:23:45:67:89:ab,
where the bytes are received left to right, and the bits within each byte are received right to left (Isb to
msb). The actual transmitted and received bits are in the order of 10000000 11000100 10100010
11100110 10010001 11010101.
BIT
BIT NAME
R/W
BIT DESCRIPTION
15..0
StationAddress-
Word0
R/W
The least significant word of the station address, corresponding to
address 0x54.
31..16
StationAddress-
Word1
R/W
The second least significant word of the station address,
corresponding to address 0x56.
47..32
StationAddress-
Word2
R/W
The most significant word of the station address, corresponding
to address 0x58.
The address comparison logic will compare the first 16 received destination address bits against
StationAddressWord0, the second 16 received destination address bits against StationAddressWord1, and
the third 16 received destination address bits against StationAddressWord2. The value set in StationAddress
is not inserted into the source address field of frames transmitted by the IP100A LF. The source address field
for every frame must be specified by the host system as part of the frame data contents.
11.4.21 TxDMABurstThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x08
Default .......................... 0x08
Width ............................ 8 bits
TxDMABurstThresh determines the threshold for when the IP100A LF makes transmit DMA bus master
requests, based upon the available space in the transmit FIFO. TxDMABurstThresh represents free
space in the transmit FIFO in multiples of 32 bytes. When the free space exceeds the threshold, the
IP100A LF may make a transmit DMA request. However, if the free space exceeds the current FragLen
subfield of the TxFrameControl field within the current TFD, the IP100A LF will make transmit DMA bus
request regardless of whether the free space exceeds the TxDMABurstThresh or not.
TxDMABurstThresh may be overridden by the TxDMAUrgentThresh mechanism. See the PCI Bus
Master Operation section for information about the relationship between TxDMABurstThresh and
TxDMAUrgentThresh. Any value less than 0x08 is invalid and is interpreted as 0x08.
BIT
BIT NAME
R/W
BIT DESCRIPTION
4..0
TxDMABurstThresh R/W
Transmit DMA Burst Threshold. The number of 32-byte words
which must be available in the transmit FIFO prior to assertion of
a transmit DMA Burst Request.
7..5
Reserved
N/A
Reserved for future use.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
