IP100A LF
Preliminary Data Sheet
48/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.2 DMACtrl
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x00
Default .......................... 0x00000000
Width ............................ 32 bits
DMACtrl controls some of the bus master functions in the receive DMA and transmit DMA logic, and
contains status bits. DMACtrl is cleared by a reset.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
RxDMAHalted
R
Receive DMA Halted. RxDMAHalted is a logic 1 whenever
receive DMA is halted by setting RxDMAHalt or an implicit halt
due to fetching a RFD with RxDMAComplete in RxFrameStatus
already a logic 1. RxDMAHalted is cleared by setting
RxDMAResume to a logic 1.
1
TxDMACmplReq
R
Transmit DMA Complete Request. TxDMACmplReq is equivalent
to the TxDMAIndicate field in the TxFrameControl of the current
TFD.
2
TxDMAHalted
R
Transmit DMA Halted. TxDMAHalted is a logic 1whenever
transmit DMA is halted by setting TxDMAHalt. TxDMAHalted is
cleared by setting TxDMAResume to a logic 1.
3
RxDMAComplete
R
Receive DMA Complete. RxDMAComplete is equivalent to the
RxDMAComplete bit in the IntStatus register. RxDMAComplete is
different from the RxDMAComplete bit in RxDMAStatus.
RxDMAComplete is latched once a frame receive DMA transfer
has completed. RxDMAComplete is cleared by acknowledging
the RxDMAComplete bit in the IntStatus register.
4
TxDMAComplete
R
TxDMAComplete. TxDMAComplete is the same as the
TxDMAComplete bit in IntStatus register. TxDMAComplete is
cleared by acknowledging the TxDMAComplete bit in the
IntStatus register.
7..5
Reserved
N/A
Reserved for future use.
8
RxDMAHalt
W
Receive DMA Halt. If RxDMAHalt is a logic 1, the receive DMA is
halted. RxDMAHalt is self-clearing and writing a 0 is ignored. See
RxDMAHalted to determine the running state of receive DMA.
9
RxDMAResume
W
Receive DMA Resume. If RxDMAResume is a logic 1, the receive
DMA is resumed. RxDMAResume is self-clearing and writing a 0
is ignored. See RxDMAHalted to determine the running state of
receive DMA.
10
TxDMAHalt
W
Transmit DMA Halt. If TxDMAHalt is a logic 1, the transmit DMA is
halted. TxDMAHalt is self-clearing and writing a 0 is ignored. See
TxDMAHalted to determine the running state of transmit DMA.
11
TxDMAResume
R/W
Transmit DMA Resume. If TxDMAResume is a logic 1, the
transmit DMA is resumed. TxDMAResume is self-clearing and
writing a 0 is ignored. See TxDMAHalted to determine the running
state of transmit DMA.
13..12
Reserved
N/A
Reserved for future use.
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