75 / 97 page
IP100A LF
Preliminary Data Sheet
75/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6
LAN PCI Configuration Registers
PCI based systems use a slot-specific block of configuration registers to perform configuration of devices
on the PCI bus. The configuration registers are accessed with PCI Configuration Cycles.
Each PCI bus device is required to decode 256 bytes of configuration registers. Of these, the first 64
bytes are pre-defined by the PCI Specification. The remaining registers may be used as needed for PCI
device-specific configuration registers. In PCI Configuration Cycles, the host system provides a
slot-specific decode signal (IDSEL) which informs the PCI device that a configuration cycle is in progress.
The PCI device responds by asserting DEVSELN, and decoding the specific configuration register from
the address bus and the byte enable signals. See the PCI Expansion ROM specification for information
on generating configuration cycles from driver software.
Figure 14 shows the PCI configuration registers implemented by IP100A LF. All locations within the
256-byte configuration space that are not shown in the table, are not implemented and return zero when
read.
BYTE 3
BYTE 2
BYTE 1
BYTE 0
ADDR
OFFSET
Data
PowerMgmtCtrl
0x54
PowerMgmtCap
NextItemPtr
Capld
0x50
0x4C
0x48
0x44
0x40
MaxLat
MinGnt
InterruptPin
InterruptLine
0x3C
0x38
CapPtr
0x34
ExpRomBaseAddress
0x30
Subsystemld
SubsystemVendorld
0x2C
CISPointer
0x28
0x24
0x20
0x1C
0x18
MemBaseAddress
0x14
IoBaseAddress
0x10
HeaderType
LatencyTimer
CacheLineSize
0x0C
ClassCode
Revisionld
0x08
ConfigStatus
ConfigCommand
0x04
Deviceld
Vendorld
0x00
FIGURE 14 : IP100A LF PCI Register Layout
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