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IP100ALF Datasheet(PDF) 78 Page - List of Unclassifed Manufacturers

Part # IP100ALF
Description  Integrated 10/100 Ethernet MAC PHY
PDF  97 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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IP100ALF Datasheet(HTML) 78 Page - List of Unclassifed Manufacturers

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IP100A LF
Preliminary Data Sheet
78/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.6 ConfigCommand
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x04
Default .......................... 0x0000
Width ............................ 16 bits
ConfigCommand provides control over the adapter’s ability to generate and respond to PCI cycles.
When a zero is written to ConfigCommand, the IP100A LF is logically disconnected from the PCI bus,
except for configuration cycles.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
IoSpace
R/W
I/O Space. When IoSpace is a logic the IP100A LF can respond
to I/O space accesses (if the IP100A LF is in the D0 power state).
1
MemorySpace
R/W
Memory
Space.
When
MemorySpace,
and
the
AddressDecodeEnable bit in the ExpRomBaseAddress register are
both a logic 1, and if the IP100A LF is in the D0 power state, the
IP100A LF is able to decode accesses to an Expansion ROM (if
present).
2
BusMaster
R/W
Bus Master. When BusMaster is a logic 1 the IP100A LF is able to
initiate bus master cycles (if the adapter is in the D0 power state).
Note: If the IP100A LF is initialized to PCI-X mode, BusMaster is
ignored when initiating Split Completions.
3
Reserved
N/A
Reserved for future use.
4
MWlEnable
R/W
Memory Write and Invalidate Enable. When MWlEnable is a logic
1 the IP100A LF is permitted to use the MWI command.
5
Reserved
N/A
Reserved for future use.
6
ParityErrorResponse R/W
Parity Error Response. When ParityErrorResponse is a logic 1
the IP100A LF responds to parity errors as defined within the PCI
specification. When ParityErrorResponse is a logic 0, the IP100A
LF ignores parity errors.
7
Reserved
N/A
Reserved for future use.
8
SERREnable
R/W
System Error Enable. When SERREnable is a logic 1, the SERRN
signal is allowed to transition as appropriate. When SERREnable is
a logic 0, the SERRN signal is a continuous logic 0.
15..9
Reserved
N/A
Reserved for future use.



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