IP100A LF
Preliminary Data Sheet
63/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.22 TxDMAListPtr
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x04
Default .......................... 0x00000000
Width ............................ 32 bits
TxDMAListPtr holds the physical address of the current transmit DMA Frame Descriptor in the transmit
DMA list. A value of zero in TxDMAListPtr is interpreted by the IP100A LF to mean that no more frames
remain to be transferred by transmit DMA. TxDMAListPtr can only point to addresses on 8-byte
boundaries, so TFD’s must be aligned on 8-byte boundaries. TxDMAListPtr may be written directly by
the host system to point the IP100A LF at the head of a newly created transmit DMA list. Writes to
TxDMAListPtr are ignored while the current value in TxDMAListPtr is non-zero. To avoid access conflicts
between the IP100A LF and the host system, the host system must set the TxDMAHalt bit of the
DMACtrl register to a logic 1 before writing to TxDMAListPtr (unless the host system has specific
knowledge that TxDMAListPtr contains zero).
BIT
BIT NAME
R/W
BIT DESCRIPTION
31..0
TxDMAListPtr
R/W
Transmit DMA List Pointer. TxDMAListPtr holds the physical
address, on a 8-byte boundary, of the current TFD in the transmit
DMA list.
The host may examine the TxDMAListPtr to determine which
frame(s) have been transferred by transmit DMA. Those frames
in the transmit DMA list before the current TxDMAListPtr have
already been transferred by transmit DMA. If the TxDMAListPtr is
zero, then all the frames have been transmitted.
11.4.23 TxDMAPollPeriod
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x0a
Default .......................... 0x00
Width ............................ 8 bits
TxDMAPollPeriod determines the interval at which the current TFD is polled. If the current TFDs,
TxDMANextPtr field is 0x00000000, the TxDMANextPtr field is polled to determine when a new TFD is
ready to be processed. Polling is disabled when TxDMAPollPeriod is 0x00. TxDMAPollPeriod represents
a multiple of 320 ns time intervals. The maximum value is 127 (or 40.64 us).
BIT
BIT NAME
R/W
BIT DESCRIPTION
6..0
TxDMAPollPeriod
R/W
Transmit DMA Poll Period. The number of 320ns intervals
between polls of the current TFD’s TxDMANextPtr field.
7
Reserved
N/A
Reserved for future use.
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