IP100A LF
Preliminary Data Sheet
57/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
2
TxInProg
R
Transmit In Progress. TxInProg provides a real-time indication
that a frame is being transmitted. If TxInProg is a logic 1, a frame
transmission is in progress. TxInProg is used by the host system
during under run recovery to delay before setting the issuing a
TxReset bit in the AsicCtrl register.
3
TxError
R
Transmit Error. If a transmit under run occurs (indicated via the
TxUnderrun bit of the TxStatus register), TxError is a logic 1,
indicating that the transmitter needs to be reset via the TxReset
bit in the AsicCtrl register.
4
Reserved
N/A
Reserved for future use.
5
StatisticsEnable
W
Statistics Enable. Writing a logic 1 to StatisticsEnable will enable
the IP100A LF’s statistic registers. The state (enabled/disabled)
of
the
IP100A
LF’s
statistic
registers
is
shown
via
StatisticsEnabled.
6
StatisticsDisable
W
Statistics Disable. Writing a logic 1 to StatisticsDisable will disable
the IP100A LF’s statistic registers. The state (enabled/disabled)
of
the
IP100A
LF’s
statistic
registers
is
shown
via
StatisticsEnabled.
7
StatisticsEnabled
R
Statistics Enabled. If StatisticsEnabled is a logic 1, the IP100A
LF’s statistic registers are enabled.
8
TxEnable
W
Transmit Enable. Writing a logic 1 to TxEnable will enable the
IP100A LF to transmit frames. The state (enabled/disabled) of the
IP100A LF’s transmitter is shown via TxEnabled.
9
TxDisable
W
Transmit Disable. Writing a logic 1 to TxDisable will disable the
IP100A LF from transmitting frames. The state (enabled/disabled)
of the IP100A LF’s transmitter is shown via TxEnabled.
10
TxEnabled
R
Transmit Enabled. If TxEnabled is a logic 1, the IP100A LF’s
transmitter is enabled.
11
RxEnable
W
Receive Enable. Writing a logic 1 to RxEnable will enable the
IP100A LF to receive frames. The state (enabled/disabled) of the
IP100A LF’s receiver is shown via RxEnabled.
12
RxDisable
W
Receive Disable. Writing a logic 1 to RxDisable will disable the
IP100A LF from receiving frames. The state (enabled/disabled) of
the IP100A LF’s receiver is shown via RxEnabled.
13
RxEnabled
R
Receive Enabled. If RxEnabled is a logic 1, the IP100A LF’s
receiver is enabled.
14
Paused
R
Paused. If Paused is a logic 1, the IP100A LF has received a
PAUSE MAC Control Frame and the IP100A LF has halted the
transmitter for the duration indicated in the PAUSE Frame’s
pause_time field. Paused will become a logic 0 when the IP100A
LF’s transmitter ends is pause operation.
15
Reserved
N/A
Reserved for future use.
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