IP100A LF
Preliminary Data Sheet
51/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.4 EepromData
Class............................. LAN I/O Registers, External Interface Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x34
Default .......................... 0x0000
Width ............................ 16 bits
EepromData is a 16-bit data register for use with the adapter’s serial EEPROM. Data from the EEPROM
should be read by the host system from EepromData register based on the state of the EepromBusy bit
of the EepromCtrl register. Data to be written to the EEPROM is written to EepromData prior to issuing
the write command to EepromCtrl.
BIT
BIT NAME
R/W
BIT DESCRIPTION
15..0
EepromData
R/W
EEPROM Data. Data read from, or to be written to, the external
EEPROM.
11.4.5 FIFOCtrl
Class............................. LAN I/O Registers, FIFO Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x3a
Default .......................... 0x0000
Width ............................ 16 bits
FIFOCtrl provides various control and indications for the transmit FIFO and the receive FIFO diagnostic.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
RAMTest Mode
R/ W
RAM Tes t Mode. I f RAMTestMode is a logic 1, the FIFO RAM is
in the test mode.
8..1
Reserved
N/A
Reserved for future use.
9
RxOverrunFrame
R/ W
Receive Overrun Frame. RxOverrunFrame determines how the
IP100A LF handles receive overrun frames. If RxOverrunFrame is a
logic 0, the IP100A LF discards all overrun frames. If
RxOverrunFrame is a logic 1, the IP100A LF will retain all overrun
frames, so that they may be inspected by the host for diagnostic
purposes.
10
Reserved
N/A
Reserved for future use.
11
RxFIFOFull
R
Receive FIFO Full. If RxFIFOFull is a logic 1, the receive FIFO is
full. RxFIFOFull does not in itself indicate an overrun condition.
However, if more data is received while RxFIFOFull is a logic 1,
an overrun will occur. RxFIFOFull is cleared as soon as the
receive FIFO is no longer full.
13..12
Reserved
N/A
Reserved for future use.
14
Transmitting
R
Transmit Indicator. Transmitting is set to a logic 1 whenever a
frame is being transmitted or during a transmit deferral).
15
Receiving
R
Receive Indicator. Receiving is set to a logic 1 whenever a frame
is being received. No action is expected on the part of the host
based on the state of Receiving.
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