IP100A LF
Preliminary Data Sheet
81/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.10 ExpRomBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x30
Default .......................... 0x00000000
Width ............................ 32 bits
ExpRomBaseAddress allows the system to define the base address for the adapter’s Expansion ROM.
ExpRomBaseAddress is disabled (read only with a value of 0x00000000) when the IP100A LF is in
Multi-Function Mode (see the Reserved/MultiFunction bit in the AsicCtrl register).
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
AddressDecode-
Enable
R/W
Address Decode Enable. If AddressDecodeEnable is a logic 0,
the
IP100A
LF’s
Expansion
ROM
is
disabled.
If
AddressDecodeEnable is a logic 1, and the MemorySpace bit in
the ConfigCommand register is a logic 1, the IP100A LF will
respond to accesses to the expansion ROM space.
14..1
Reserved
N/A
Reserved for future use.
31..15
RomBaseAddress
R/W
ROM Base Address. RomBaseAddress contains the expansion
ROM base address, or the upper 16 bits (or 15 bits, depending on
the state of the ExpRomSize bit in the AsicCtrl register) of the
Expansion ROM address range.
If the ExpRomSize bit in the AsicCtrl register is a logic 0, all 16
bits of RomBaseAddress are valid. If the ExpRomSize bit in the
AsicCtrl register is a logic 1, bits 31 through 16 of
RomBaseAddress are valid, with bit 15 ignored (set to a logic 0)
during write operations.
11.6.11 HeaderType
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0e
Default .......................... 0x00 (single function)/0x80 (multi-function)
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
HeaderType
R
Header Type. If the Reserved/MultiFunction bit in the AsicCtrl
register is a logic 0, HeaderType is set to 0x00 identifying the
IP100A LF as a single-function PCI device and specifying the
configuration register layout.
If the Reserved/MultiFunction bit in the AsicCtrl register is a logic
1, HeaderType is set to 0x80 identifying the IP100A LF as a
multi-function PCI device and specifying the configuration register
layout.
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