IP100A LF
Preliminary Data Sheet
set the address directly. Then, by setting the ReceiveUnicast bit in the ReceiveMode register, the IP100A
LF will receive unicast frames whose destination address matches the value in the StationAddress
register.
The ReceiveMulticastHash bit in ReceiveMode enables a filtering mechanism for Ethernet multicast
frames. This filtering mechanism uses a 64-bit hash table (HashTable register) for selective reception of
Ethernet multicast frames.
Additionally, Ethernet frames containing IP multicast destination addresses can also be received by
setting the ReceiveIPMulticast bit in the ReceiveMode register. IP multicast, or Host Extension for IP
Multicasting, datagrams map to frames with Ethernet destination addresses of 0x01005e****** (where *
represents any hexadecimal value).
The MACCtrl0 and MACCtrl1 registers are used to configure parameters including full duplex, flow
control, and statistics gathering.
In half duplex mode, the IP100A LF implements the CSMA/CD algorithm. If multiple nodes on the same
network attempt to transmit simultaneously, a collision will occur resulting in re-transmission. In full
duplex mode, the IP100A LF can transmit and receive frames simultaneously without incurring collisions.
To configure the IP100A LF for full duplex mode operation, the host system must detect a full duplex
physical link via the PHY Status Register, and must set the FullDuplexEnable bit in the MACCtrl0
register.
The IEEE 802.3x Full Duplex standard defines a special frame known as the PAUSE MAC Control frame.
The PAUSE frame is used to implement flow control in full duplex networks allowing stations on opposite
ends of a full duplex link the ability to inhibit transmission of data frames for a specified period of time.
The PAUSE frame format is defined as shown in Figure 3.
DA
SA
TYPE
OPCODE
PAUSE TIME
PAD
FIELD
6
6
2
2
2
42
0x0180C2000001
0x8808
0x0001
LENGTH
(BYTES)
FIGURE 3: PAUSE Frame
Whenever the FlowControlEnable bit in the MACCtrl0 register is set, the IP100A LF looks for any
incoming PAUSE frame. If found, the IP100A LF inhibits transmission of all data frames for the time
specified in the two-byte pause_time field. The pause_time field is specified in slot times relative to the
current data rate; one slot time is 51.2 us at 10 Mbps, and 5.12 us at 100 Mbps. The transmission of
PAUSE frames is the responsibility of the host. The MAC Control frame must be constructed by the host
and placed into the TxFIFO. For end station applications, host system should only accept PAUSE frames,
and not generate them. Flow control is designed to originate from network devices such as switches.
7.3
TxDMA and Frame Transmission
The TxDMA Logic transfers frame data from the host system memory to the IP100A LF based on a
March. 30, 2007
17/97
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
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