IP100A LF
Preliminary Data Sheet
85/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.6.20 PowerMgmtCap
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x52
Default Value ................ 0x7602
Width ............................ 16 bits
PowerMgmtCap provides information about the IP100A LF’s power management capabilities. Several
bits are loaded from the EEPROM during auto-initialization.
BIT
BIT NAME
R/W
BIT DESCRIPTION
2..0
Versi on
R
Version. Version is set to 0x2, indicating PCI Bus Power
Management Specification Revision 1.1.
3
Reserved
N/A
Reserved for future use.
4
Vaux
R
Auxiliary Voltage. If Vaux is a logic 1, auxiliary power via the PCI
Bus is required from the system to support PME in the D3cold
state. If Vaux is a logic 0, auxiliary power is supplied from
elsewhere (i.e. not from the PCI Bus) to support PME in the
D3cold state.
8..5
Reserved
N/A
Reserved for future use.
9
D1Support
R
D1 Power State Support. When D1Support is a logic 1, the
IP100A LF supports the D1 power state. D1Support is loaded
from the ConfigParm field of an EEPROM during auto
initialization of the IP100A LF.
10
D2Support
R
D2 Power State Support. When D2Support is a logic 1, the
IP100A LF supports the D2 power state. D2Support is loaded
from the ConfigParm field of an EEPROM during auto
initialization of the IP100A LF.
15..11
PmeSupport
R
Power Management Event Support. PmeSupport indicates the
power states from which the IP100A LF is able to generate a
power management event by asserting the PMEN signal. Each bit
corresponds to a power state. A logic 1 in a particular bit position
indicates that events can be generated from the indicated power
state.
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
POWER MANAGEMENT EVENT
MAY BE GENERATED FROM
STATE
x
x
x
x
1
D0
x
x
x
1
x
D1
x
x
1
x
x
D2
x
1
x
x
x
D3Hot
1
x
x
x
x
D3Cold
PmeSupport bit 11 and 14 are hard-wired to 0 and 1 respectively,
while bits 12, 13, and 15 are loaded from the ConfigParm field of
an EEPROM during auto initialization of the IP100A LF.
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