IP100A LF
Preliminary Data Sheet
74/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.5.15 OctetsTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x6c
Default .......................... 0x00000000
Width ............................ 32 bits (accessible as 2, 16 bit words)
BIT
BIT NAME
R/W
BIT DESCRIPTION
19..0
OctetsTransmitted-
Ok
R/W
Octets Transmitted OK is a count of data and padding octets of
frames successfully transmitte cm d. OctetsTransmittedOk will
wrap around to zero after reaching 0xFFFFFFFF. See IEEE
802.3 Clause 30.3.1.1.8.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when OctetsTransmittedOk reaches a value of
0xC0. OctetsTransmittedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of OctetsTransmittedOk also clears the register.
31..20
Reserved
N/A
Reserved for future use.
11.5.16 SingleCollisionFrames
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x77
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
BIT DESCRIPTION
7..0
Single Collision
Frames
R/W
Single Collision Frames is a count of the number of frames that
are involved in a single collision, and are subsequently
transmitted successfully. SingleCollisionFrames will wrap around
to zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.3.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when SingleCollisionFrames reaches a value
of 0xC0. SingleCollisionFrames is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl1 register.
A read of SingleCollisionFrames also clears the register.
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