IP100A LF
Preliminary Data Sheet
52/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.6 HashTable
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x66, 0x64, 0x62, 0x60
Default .......................... 0x0000000000000000
Width ............................ 64 bits (accessible as 4, 16 bit words)
The host system stores a 64-bit hash table in this register for selectively receiving multicast frames.
Setting the ReceiveMulticastHash bit in ReceiveMode register enables the filtering mechanism.
BIT
BIT NAME
R/W
BIT DESCRIPTION
15..0
HashTableWord0
R/W
The least significant word of the hash table, corresponding to
address 0x60.
31..16
HashTableWord1
R/W
The second least significant word of the hash table,
corresponding to address 0x62.
47..32
HashTableWord2
R/W
The second most significant word of the hash table,
corresponding to address 0x64.
63..48
HashTableWord3
R/W
The most significant word of the hash table, corresponding to
address 0x66.
The IP100A LF applies a cyclic-redundancy-check (the same CRC used to calculate the frame data FCS)
to the destination address of all incoming multicast frames (with multicast bit set). The low-order 6 bits of
the CRC result are used as an addressing index into the hash table. The MSB of HashTable[3] is the
most significant bit, and the LSB of HashTable[0] is the least significant bit, addressed by the 6-bit index.
If the HashTable bit addressed by the index is a logic 1, the frame is accepted by the IP100A LF and
transferred to higher layers. If the addressed hash table bit is a logic 0, the frame is discarded.
11.4.7 IntEnable
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x4c
Default .......................... 0x0000
Width ............................ 16 bits
Enables individual interrupts as specified in the IntStatus register. Setting a bit in IntEnable will allow the
specific source to generate an interrupt on the PCI bus. IntEnable is cleared by a read of IntStatusAck.
BIT
BIT NAME
R/W
BIT DESCRIPTION
0
Reserved
N/A
Reserved for future use.
1
EnHostError
R/W
Enable Host Error Interrupt. Enables the HostError interrupt.
2
EnTxComplete
R/W
Enable Transmit Complete Interrupt. Enables the TxComplete
interrupt.
3
EnMACControlFrame R/W
Enable
MAC
Control
Frame
Interrupt.
Enables
the
MACControlFrame interrupt.
4
EnRxComplete
R/W
Enable Receive Complete Interrupt. Enables the RxComplete
interrupt.
5
Reserved
R/W
Reserved for future use.
6
EnIntRequested
R/W
Enable Interrupt Requested Interrupt. Enables the IntRequested
interrupt.
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