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Table 108. i.MX 93 Data Sheet document revision history...continued

Document ID

Release

date

Description

• Updated LVDS Ball name in Table 4

• Replace the text from "The power architecture of i.MX93 is defined based on the

assumption that a PMIC is used to supply all the power rails to the SoC. The SoC

can be powered from discrete parts rather than a PMIC, but a discrete-based solution

is not necessarily BOM cost-optimized." to "The i.MX power architecture is designed

with the expectation that a dedicated PMIC supplies all required power rails, ensuring

compliance with stringent power-up and power-down sequencing requirements. While

discrete component-based implementations are technically viable, they typically lead to

increased BOM cost, greater design complexity, and a larger PCB footprint. In contrast, the

proposed PMIC solution is BOM-optimized, minimizes board area by integrating multiple

power functions into a single package, and simplifies system design by providing a

validated, production-tested power management solution that inherently meets the voltage

and sequencing specifications of the i.MX platform." in Power architecture section.

• Updated Figure 3

IMX93CEC v.6.1 07 July

2025

• Removed the I/O pin information from Ordering information

• Updated the Package type in Figure 1

• Removed Section 14 x 14 mm package information

IMX93CEC v.6.0 04 June

2025

• Updated Ordering information

• Updated Figure 1

• Updated the descriptions about DRAM and LPUART, and ADC in Table 1; Removed

FlexIO from Table 1

• Added LPDDR4 in Figure 2; updated ADC and LPUART in Figure 2

• Updated the description about ONOFF and XTALI_24/XTALO_24M in Table 3

• Added Table 12

• Updated Table 16

• Updated Table 28

• Updated the description of DDR SDRAM–specific parameters (LPDDR4/LPDDR4X) and

Clock/data/command/address pin allocations

• Added a footnote in Table 44

• Added a footnote in Table 51

• Updated the unit of Csample, Ccompare, and Cconversion to cycle in Table 52; removed the

maximum value of Ccompare and second ADC clock in Table 52; added ENOB lavues in

Table 52

• Removed Table. ADC electrical specifications (VREFH = VDD_ANAx_1p8 and

VADINmax ≤ VREFH)

• Added a footnote in Table 69

• Updated Table 72

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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