IMX93CEC datasheet(114/123 Pages) NXP

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Table 107. DDR pin function list ...continued

DRAM_MTRST1

—

DRAM_CKE0_A

CKEA[0]

DRAM_CKE1_A

CKEA[1]

DRAM_CS0_A

CSA[0]

DRAM_CS1_A

CSA[1]

DRAM_CK_T_A

CLKA_T

DRAM_CK_C_A

CLKA_C

DRAM_CA0_A

CAA[0]

DRAM_CA1_A

CAA[1]

DRAM_CA2_A

CAA[2]

DRAM_CA3_A

CAA[3]

DRAM_CA4_A

CAA[4]

DRAM_CA5_A

CAA[5]

DRAM_ZQ[1]

—

[1] DRAM_ZQ can be connected with a 120 Ω ±1% resistor to GND.

7 Revision history

Table 108 provides a revision history for this data sheet.

Table 108. i.MX 93 Data Sheet document revision history

Document ID

Release

date

Description

IMX93CEC v.7

12 Feb

2026

• Added note in DDR mode

• Added note in SDR mode

• Updated Table 25

• Updated Table 28

• Updated footnote information for "Vin/Vout" in Table 8

• Added note in SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

• Added note in DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

• Updated "DRAM_CAx_C to DRAM_CAx_A" in DDR pin function list section.

• Updated features information for Audio in Table 1

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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