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XC2000 Datasheet(PDF) 118 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 118 Page - Infineon Technologies AG |
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118 / 647 page  XC2000 Derivatives System Units (Vol. 1 of 2) Memory Organization Preliminary User’s Manual 3-56 V1.0, 2007-06 MemoryX2K, V1.1 Field Bits Typ Description IEN 0 rw Interrupt Enable If set, the interrupt signal of the IMB gets activated when ISR is set. DIDTRP 1 rw Disable Instruction Fetch Double Bit Error Trap If set, a double bit ECC error does not cause the replacement of the fetched data by a trap instruction. DDDTRP 2 rw Disable Data Read Double Bit Error Trap If set, a double bit ECC error during data read does not trigger the Flash access hardware trap. DPROTRP 3 rw Disable Protection Trap If set, a read request from read protected flash memory does not trigger the Flash access hardware trap. ICLR 8 w Interrupt Clear When written with 1 the ISR is cleared. Reading this bit delivers always 0. Writing a 0 is ignored. ISET 9 w Interrupt Set When written with 1 the ISR is set and if IEN is set the interrupt signal is activated. Reading this bit delivers always 0. Writing a 0 is ignored. When writing ISET and ICLR to 1 concurrently ISET takes priority so ISR is set. PSERCLR 10 w Clear PSRAM Error Flag When written with 1 the PSER is cleared. Reading this bit delivers always 0. Writing a 0 is ignored. PSER 14 rh PSRAM Error Flag This flag is set when write requests to the write protected or not implemented PSRAM range are detected. This flag can be cleared by writing 1 to PSERCLR. ISR 15 rh Interrupt Service Request If set, it indicates that at least one IMB_FSR.BUSY bit changed from 1 to 0. If IEN was set an interrupt request is sent to the interrupt controller. After servicing the interrupt the software handler clears this flag by writing a 1 to ICLR. |
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