SH7616 datasheet(120/935 Pages) RENESAS

120 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 94 of 906

REJ09B0292-0200

Table 2.33 Correspondence between DSP Instruction Operands and Registers

ALU and BPU Instructions

Multiplication Instructions

Yes

—

Yes

—

Yes

—

Yes

—Yes

Yes

—

——Yes

—Yes

Yes

—

——Yes

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

When writing parallel instructions, write the B field instructions first, then write the A field

instructions:

PADD A0,M0,A0 PMULS X0,Y0,M0

MOVX.W @R4+,X0

MOVY.W @R6+,Y0[;]

DCF PINC X1,A1

MOVX.W A0,@R5+R8

MOVY.W @R7+,Y0[;]

PCMP X1,M0

MOVX.W @R4+R8

[NOPY][;]

Text in brackets ([]) can be omitted. The no operation instructions NOPX and NOPY can be

omitted. Semicolons (;) are used to demarcate instruction lines, but can be omitted. If semicolons

are used, the space after the semicolon can be used for comments.

The individual status codes (DC, N, Z, V, GT) of the DSR register are always updated by

unconditional ALU operation instructions and shift operation instructions. Conditional instructions

do not update the status codes, even if the conditions have been met. Multiplication instructions

also do not update the status codes. DC bit definitions are determined by the specifications of the

CS bits in the DSR register.

Table 2.34 lists the DSP operation instructions by classification.

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