SH7616 datasheet(117/935 Pages) RENESAS

117 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 91 of 906

REJ09B0292-0200

Table 2.30 Single Data Transfer Instructions

Instruction

Operation

Code

Cycles

DC Bit

MOVS.W

@-As,Ds

As–2

→As,(As)→MSW of

Ds,0

→LSW of Ds

111101AADDDD0000

1—

MOVS.W @As,Ds

(As)

→MSW of Ds,0→LSW of

111101AADDDD0100

1—

MOVS.W

@As+,Ds

(As)

→MSW of Ds,0→LSW of

Ds, As+2

→As

111101AADDDD1000

1—

MOVS.W

@As+Ix,Ds

(As)

→MSW of Ds,0→LSW of

Ds, As+Ix

→As

111101AADDDD1100

1—

MOVS.W

Ds,@-As

As–2

→As,MSW of Ds→(As)*

111101AADDDD0001

1—

MOVS.W Ds,@As

MSW of Ds

→(As)*

111101AADDDD0101

1—

MOVS.W

Ds,@As+

MSW of Ds

→(As)*,As+2→As

111101AADDDD1001

1—

MOVS.W

Ds,@As+Is

MSW of Ds

→(As)*,As+Is→As

111101AADDDD1101

1—

MOVS.L

@-As,Ds

As–4

→As,(As)→Ds

111101AADDDD0010

1—

MOVS.L @As,Ds

(As)

→Ds

111101AADDDD0110

1—

MOVS.L

@As+,Ds

(As)

→Ds,As+4→As

111101AADDDD1010

1—

MOVS.L

@As+Is,Ds

(As)

→Ds,As+Is→As

111101AADDDD1110

1—

MOVS.L Ds,

@-As

As–4

→As,Ds→(As)*

111101AADDDD0011

1—

MOVS.L Ds,@As

→(As)*

111101AADDDD0111

1—

MOVS.L

Ds,@As+

→(As)*,As+4→As

111101AADDDD1011

1—

MOVS.L

Ds,@As+Is

→(As)*,As+Is→As

111101AADDDD1111

1—

Note: * When guard bit registers A0G and A1G are specified for the source operand Ds, data is

sign-extended before being transferred.

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