SH7616 datasheet(115/935 Pages) RENESAS

115 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 89 of 906

REJ09B0292-0200

Instruction

Code

Operation

Cycles

T Bit

STS.L

X1,@-Rn

0100nnnn10010010

Rn–4

→Rn,X1→(Rn)

—

STS

Y0,Rn

0000nnnn10101010

→Rn

—

STS.L

Y0,@-Rn

0100nnnn10100010

Rn–4

→Rn,Y0→(Rn)

—

STS

Y1,Rn

0000nnnn10111010

→Rn

—

STS.L

Y1,@-Rn

0100nnnn10110010

Rn–4

→Rn,Y1→(Rn)

—

SETRC

0100mmmm00010100

Rm[11:0]

→RC (SR[27:16]) 1

—

SETRC

#imm

10000010iiiiiiii

imm

→RC(SR[23:16]),

→SR[27:24]

1—

LDRS

@(disp,PC)

10001100dddddddd

disp

× 2+PC→RS

—

LDRE

@(disp,PC)

10001110dddddddd

disp

× 2+PC→RE

—

2.5.2

DSP Data Transfer Instruction Set

Table 2.27 lists the DSP data transfer instructions by classification.

Table 2.27 Classification of DSP Data Transfer Instructions

Classification

Types

Operation

Code

Function

No. of

Instructions

NOPX

X memory no operation

MOVX

X memory data transfer

Double

datatransferinstr

uctions

NOPY

Y memory no operation

MOVY

Y memory data transfer

Single data

transfer

instructions

MOVS

Single data transfer

Total: 5

Total: 30

The data transfer instructions are divided into two groups, double data transfers and single data

transfers. Double data transfers can be combined with DSP operation instructions to perform DSP

parallel processing. The parallel processing instructions are 32 bit length, and the double data

transfer instructions are incorporated into their A fields. Double data transfers that are not parallel

processing instructions are 16 bit length, as are the single data transfer instructions.

The X memory and Y memory can be accessed simultaneously in parallel in double data transfers.

One instruction each is designated from among the X and Y memory data accesses. The Ax

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