SH7616 datasheet(112/935 Pages) RENESAS

112 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 86 of 906

REJ09B0292-0200

Instruction

Instruction Code

Operation

Cycles T Bit

STS

MACH,Rn

0000nnnn00001010

MACH

→ Rn

—

STS

MACL,Rn

0000nnnn00011010

MACL

→ Rn

—

STS

PR,Rn

0000nnnn00101010

→ Rn

—

STS

DSR,Rn

0000nnnn01101010

DSR

→ Rn

—

STS

A0,Rn

0000nnnn01111010

→ Rn

—

STS

X0,Rn

0000nnnn10001010

→ Rn

—

STS

X1,Rn

0000nnnn10011010

→ Rn

—

STS

Y0,Rn

0000nnnn10101010

→ Rn

—

STS

Y1,Rn

0000nnnn10111010

→ Rn

—

STS.L

MACH,@–Rn

0100nnnn00000010

Rn–4

→ Rn, MACH → (Rn)

—

STS.L

MACL,@–Rn

0100nnnn00010010

Rn–4

→ Rn, MACL → (Rn)

—

STS.L

PR,@–Rn

0100nnnn00100010

Rn–4

→ Rn, PR → (Rn)

—

STS.L

DSR,@–Rn

0100nnnn01100010

Rn–4

→ Rn, DSR → (Rn)

—

STS.L

A0,@–Rn

0100nnnn01110010

Rn–4

→ Rn, A0 → (Rn)

—

STS.L

X0,@–Rn

0100nnnn10000010

Rn–4

→ Rn, X0 → (Rn)

—

STS.L

X1,@–Rn

0100nnnn10010010

Rn–4

→ Rn, X1 → (Rn)

—

STS.L

Y0,@–Rn

0100nnnn10100010

Rn–4

→ Rn, Y0 → (Rn)

—

STS.L

Y1,@–Rn

0100nnnn10110010

Rn–4

→ Rn, Y1 → (Rn)

—

TRAPA

#imm

11000011iiiiiiii

PC/SR

→ stack area, (imm ×

4 + VBR)

→ PC

8—

Note: * The number of execution cycles before the chip enters sleep mode.

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