SH7616 datasheet(113/935 Pages) RENESAS

113 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 87 of 906

REJ09B0292-0200

Precautions Concerning the Number of Instruction Execution Cycles: The execution cycles

listed in the tables are minimum values. In practice, the number of execution cycles increases

under such conditions as 1) when the instruction fetch is in contention with a data access, 2) when

the destination register of a load instruction (memory

→ register) is the same as the register used

by the next instruction, 3) when the branch destination address of a branch instruction is a 4n + 2

address.

CPU Instructions That Support DSP Functions: A number of system control instructions have

been added to the CPU core instructions to support DSP functions. The RS, RE and MOD

registers have been added to support repeat control and modulo addressing, and the repeat counter

(RC) has been added to the status register (SR). The LDC and STC instructions have been added

in order to access the aforementioned. The LDS and STS instructions have been added in order to

access the DSP registers DSR, A0, X0, X1, Y0 and Y1.

The SETRC instruction has been added to set the repeat counter (RC, bits 27 to 16) and repeat

flags (RF1, RF0, bits 3 and 2) of the SR register. When the SETRC instruction operand is

immediate, the 8-bit immediate data is stored in bits 23 to 16 of the SR register and bits 27 to 24

are cleared to 0. When the operand is a register, bits 11 to 0 (12 bits) of the register are stored in

bits 27 to 16 of the SR register. Additionally, the status of 1 instruction repeat (00), 2 instruction

repeat (01), 3 instruction repeat (11) or 4 instruction or greater repeat (10) is set from the RS and

RE set values.

In addition to the LDC instruction, the LDRS and LDRE instructions have been added for

establishing the repeat start and repeat end addresses in the RS and RE registers.

The added instructions are listed in table 2.26.

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