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SH7616 Datasheet(PDF) 114 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 114 Page - Renesas Technology Corp |
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114 / 935 page  Section 2 CPU Rev. 2.00 Mar 09, 2006 page 88 of 906 REJ09B0292-0200 Table 2.26 Added CPU Instructions Instruction Code Operation Cycles T Bit LDC Rm,MOD 0100mmmm01011110 Rm →MOD 1 — LDC Rm,RE 0100mmmm01111110 Rm →RE 1 — LDC Rm,RS 0100mmmm01101110 Rm →RS 1 — LDC.L @Rm+,MOD 0100mmmm01010111 (Rm) →MOD,Rm+4→Rm 3 — LDC.L @Rm+,RE 0100mmmm01110111 (Rm) →RE,Rm+4→Rm 3 — LDC.L @Rm+,RS 0100mmmm01100111 (Rm) →RS,Rm+4→Rm 3 — STC MOD,Rn 0000nnnn01010010 MOD →Rn 1 — STC RE,Rn 0000nnnn01110010 RE →Rn 1 — STC RS,Rn 0000nnnn01100010 RS →Rn 1 — STC.L MOD,@-Rn 0100nnnn01010011 Rn–4 →Rn,MOD→(Rn) 2 — STC.L RE,@-Rn 0100nnnn01110011 Rn–4 →Rn,RE→(Rn) 2 — STC.L RS,@-Rn 0100nnnn01100011 Rn–4 →Rn,RS→(Rn) 2 — LDS Rm,DSR 0100mmmm01101010 Rm →DSR 1 — LDS.L @Rm+,DSR 0100mmmm01100110 (Rm) →DSR,Rm+4→Rm 1 — LDS Rm,A0 0100mmmm01111010 Rm →A0 1 — LDS.L @Rm+,A0 0100mmmm01110110 (Rm) →A0,Rm+4→Rm 1 — LDS Rm,X0 0100mmmm10001010 Rm →X0 1 — LDS.L @Rm+,X0 0100mmmm10000110 (Rm) →X0,Rm+4→Rm 1 — LDS Rm,X1 0100mmmm10011010 Rm →X1 1 — LDS.L @Rm+,X1 0100mmmm10010110 (Rm) →X1,Rm+4→Rm 1 — LDS Rm,Y0 0100mmmm10101010 Rm →Y0 1 — LDS.L @Rm+,Y0 0100mmmm10100110 (Rm) →Y0,Rm+4→Rm 1 — LDS Rm,Y1 0100mmmm10111010 Rm →Y1 1 — LDS.L @Rm+,Y1 0100mmmm10110110 (Rm) →Y1,Rm+4→Rm 1 — STS DSR,Rn 0000nnnn01101010 DSR →Rn 1 — STS.L DSR,@-Rn 0100nnnn01100010 Rn–4 →Rn,DSR→(Rn) 1 — STS A0,Rn 0000nnnn01111010 A0 →Rn 1 — STS.L A0,@-Rn 0100nnnn01110010 Rn–4 →Rn,A0→(Rn) 1 — STS X0,Rn 0000nnnn10001010 X0 →Rn 1 — STS.L X0,@-Rn 0100nnnn10000010 Rn–4 →Rn,X0→(Rn) 1 — STS X1,Rn 0000nnnn10011010 X1 →Rn 1 — |
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