SH7616 datasheet(207/935 Pages) RENESAS

207 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 181 of 906

REJ09B0292-0200

5.3.24

Vector Number Setting Register R (VCRR)

Vector number setting register R (VCRR) is a 16-bit read/write register that sets the serial I/O 1

(SIO1) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0–

127).

VCRR is initialized to H'0000 by a reset. It is not initialized in standby mode.

Bit:

—

RER1V6 RER1V5 RER1V4 RER1V3 RER1V2 RER1V1 RER1V0

Initial value:

00000000

R/W:

R/W

Bit:

76543210

—

TER1V6 TER1V5 TER1V4 TER1V3 TER1V2 TER1V1 TER1V0

Initial value:

00000000

R/W:

R/W

Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.

Bits 14 to 8—Serial I/O 1 (SIO1) Receive Overrun Error Interrupt Vector Number 6 to 0

(RER1V6–RER1V0): These bits set the vector number for the serial I/O 1 (SIO1) receive overrun

error interrupt. There are seven bits, so the value can be set between 0 and 127.

Bits 6 to 0—Serial I/O 1 (SIO1) Transmit Underrun Error Interrupt Vector Number 6 to 0

(TER1V6–TER1V0): These bits set the vector number for the serial I/O 1 (SIO1) transmit

underrun error interrupt. There are seven bits, so the value can be set between 0 and 127.

SH7616 Datasheet(PDF) 207 Page - Renesas Technology Corp