SH7616 datasheet(211/935 Pages) RENESAS

211 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 185 of 906

REJ09B0292-0200

Table 5.6

Interrupt Request Sources and Vector Number Setting Registers (1)

Bits

14–8

6–0

Vector number setting register

WDT

Interval interrupt (WDT)

Compare-match interrupt

(BSC)

Vector number setting register A

E-DMAC interrupt (E-DMAC)

Reserved

Vector number setting register B

Reserved

Vector number setting register C

Input-capture interrupt (FRT)

Output-compare interrupt

(FRT)

Vector number setting register D

Overflow interrupt (FRT)

Reserved

Vector number setting register E

Input capture/compare match

interrupt (TPU0/TGR0A)

Input capture/compare match

interrupt (TPU0/TGR0B)

Vector number setting register F

Input capture/compare match

interrupt (TPU0/TGR0C)

Input capture/compare match

interrupt (TPU0/TGR0D)

Vector number setting register G

Overflow interrupt

(TPU0/TCNT0)

Reserved

Vector number setting register H

Input capture/compare match

interrupt (TPU1/TGR1A)

Input capture/compare match

interrupt (TPU1/TGR1B)

Vector number setting register I

Overflow interrupt

(TPU1/TCNT1)

Underflow interrupt

(TPU1/TCNT1)

Vector number setting register J

Input capture/compare match

interrupt (TPU2/TGR2A)

Input capture/compare match

interrupt (TPU2/TGR2B)

Vector number setting register K

Overflow interrupt

(TPU2/TCNT2)

Underflow interrupt

(TPU2/TCNT2)

Vector number setting register L

Receive-error interrupt (SCIF1) Receive-data-full/data-ready

interrupt (SCIF1)

Vector number setting register M

Break interrupt (SCIF1)

Transmit-data-empty interrupt

(SCIF1)

Vector number setting register N

Receive-error interrupt (SCIF2) Receive-data-full/data-ready

interrupt (SCIF2)

Vector number setting register O

Break interrupt (SCIF2)

Transmit-data-empty interrupt

(SCIF2)

Vector number setting register P

Receive overrun error interrupt

(SIOF)

Transmit underrun error

interrupt (SIOF)

Vector number setting register Q

Receive-data-full interrupt

(SIOF)

Transmit-data-empty interrupt

(SIOF)

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