SH7616 datasheet(215/935 Pages) RENESAS

215 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 189 of 906

REJ09B0292-0200

Bits 15 to 8—IRQ Sense Select Bits (IRQ31S–IRQ00S): These bits set the IRQ detection mode

for

IRL3–IRL0.

Bit 15–8:

IRQn1S

Bit 15–8:

IRQn0S

Description

Low-level detection

(Initial value)

Rising-edge detection

Falling-edge detection

Both-edge detection

Note: n = 0 to 3

Bits 7 to 4—IRL Pin Status Bits (IRL3PS–IRL0PS): These bits indicate the

IRL3–IRL0 pin status.

The

IRL3–IRL0 pin levels can be ascertained by reading these bits. These bits cannot be modified.

Bit 7–4: IRLnPS

Description

Low level is being input to pin

IRLn

High level is being input to pin

IRLn

Note: n = 0 to 3

Bits 3 to 0—IRQ3 to IRQ0 Flags (IRQ3F–IRQ0F): These bits indicate the IRQ3–IRQ0 interrupt

request status.

Bit 3–0:

IRQ3F–IRQ0F

Detection Setting

Description

Level detection

There is no IRQn interrupt request

(Initial value)

[Clearing condition]

When

IRLn input is high

Edge detection

An IRQn interrupt request has not been detected

(Initial value)

[Clearing conditions]

• When 0 is written to IRQnF after reading IRQnF = 1

• When an IRQn interrupt is accepted

Level detection

There is an IRQn interrupt request

[Setting condition]

When

IRLn input is low

Edge detection

An IRQn interrupt request has been detected

[Setting condition]

When an

IRLn input edge is detected

Note: n = 0 to 3

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