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SH7616 Datasheet(PDF) 217 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 217 Page - Renesas Technology Corp |
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217 / 935 page ![]() Section 5 Interrupt Controller (INTC) Rev. 2.00 Mar 09, 2006 page 191 of 906 REJ09B0292-0200 No Yes NMI? No Yes User break? No Yes No H-UDI interrupt? Yes Level 15 interrupt? No Yes I3 to I0 ≤ level 14? No Yes Level 14 interrupt? No Yes Yes I3 to I0 ≤ level 13? No Yes Level 1 interrupt? No Yes I3 to I0 = level 0? No Program execution state Save SR to stack Save PC to stack Read vector number* Branch to exception service routine Interrupt generated? Copy accepted interrupt level to I3–I0 Read exception vector table I3–I0: Status register interrupt mask bits. Note: * The vector number is only read from an external source when an external vector number is specified for the IRL/IRQ interrupt vector number. Figure 5.8 Interrupt Sequence Flowchart |
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