SH7616 datasheet(220/935 Pages) RENESAS

220 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 194 of 906

REJ09B0292-0200

5.6

Sampling of Pins

IRL3

IRL3–IRL0

IRL0

Signals on interrupt pins

IRL3 to IRL0 pass through the noise canceler before being sent by the

interrupt controller to the CPU as interrupt requests, as shown in figure 5.10. The noise canceler

cancels noise that changes in short cycles. The CPU samples the interrupt requests between

executing instructions. During this period, the noise canceler output changes according to the

noise-eliminated pin level, so the pin level must be held until the CPU samples it. This means that

interrupt sources generally must not be cleared inside interrupt routines.

When an external vector is fetched, the interrupt source can also be cleared when the external

vector fetch cycle is detected.

Interrupt acceptance

signal from CPU

Interrupt request

to CPU

Noise canceler

output

Cleared when interrupt is accepted

IRL3–IRL0

pin level

1011 for

1 clock

due to

noise

Level 2 interrupt

Level 6 interrupt

1111

1101

1001

1111

1101

1001

IRL0

IRL1

IRL2

IRL3

CPU

Interrupt

controller

Noise

canceler

Interrupt

request

Interrupt

accepted

Figure 5.10

IRL3

IRL3–IRL0

IRL0

IRL0 Pin Sampling

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