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SH7616 Datasheet(PDF) 224 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 224 Page - Renesas Technology Corp |
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224 / 935 page ![]() Section 5 Interrupt Controller (INTC) Rev. 2.00 Mar 09, 2006 page 198 of 906 REJ09B0292-0200 Interrupt clear instruction On-chip peripheral write, min. 1 Icyc Write completed Next interrupt can be accepted Synchronization instruction • • • On-chip peripheral interrupt LDC instruction Interrupt disable instruction Normal instruction DE M M DE W DE DE DE 0.5Icyc + 1.0Pcyc On-chip peripheral read, min. 1 Icyc Figure 5.14 Pipeline Operation when Interrupts are Enabled by Means of SR Modification In the above figure, the stage in which the instruction fetch occurs cannot be specified because of the mix of DSP instructions in this chip, so instruction fetch F is omitted in most cases during pipeline operation. |
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