SH7616 datasheet(222/935 Pages) RENESAS

222 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 196 of 906

REJ09B0292-0200

Interrupt clear instruction

External write

cycle

External read

cycle

Write completed

Next interrupt can be accepted

Synchronization instruction

RTE instruction

IRL3–IRL0

Delay slot instruction

Interrupt return destination instruction

0.5Icyc + 1.0Ecyc + 1.5Pcyc

F: Instruction fetch ............... Instruction is fetched from memory in which program is stored

D: Instruction decode ........... Fetched instruction is decoded

E: Instruction execution ........ Data operation or address operation is performed in accordance

with result of decoding

M: Memory access ................ Memory data access is performed

W: Write-back ....................... Data read from memory is written to register

Figure 5.11 Pipeline Operation when Returning by Means of RTE Instruction

Interrupt clear instruction

External write

cycle

External read

cycle

Write completed

Next interrupt can be accepted

Synchronization instruction

•

IRL3–IRL0

LDC instruction

Interrupt disable instruction

Normal instruction

0.5Icyc + 1.0Ecyc + 1.5Pcyc

Figure 5.12 Pipeline Operation when Interrupts are Enabled by Means of SR Modification

When an interrupt source is cleared by the program, pipeline operation must be considered

to ensure that the same interrupt is not implemented again.

SH7616 Datasheet(PDF) 222 Page - Renesas Technology Corp