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SH7616 Datasheet(PDF) 219 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 219 Page - Renesas Technology Corp |
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219 / 935 page ![]() Section 5 Interrupt Controller (INTC) Rev. 2.00 Mar 09, 2006 page 193 of 906 REJ09B0292-0200 Table 5.8 Interrupt Response Time Number of States Peripheral Module Item NMI IRL/IRQ A B Notes Compare identified interrupt priority with SR mask level 2.0 × Icyc 0.5 × Icyc + 1.0 × Ecyc + 1.5 × Pcyc 0.5 × Icyc + 1.0 × Pcyc 1.0 × Pcyc Wait for completion of sequence currently being executed by CPU X ( ≥ 0) X ( ≥ 0) X ( ≥ 0) X ( ≥ 0) The longest sequence is for interrupt or address- error exception handling (X = 4.0 × Icyc + m1 + m2 + m3 + m4). If an interrupt-making instruction follows, however, the time may be even longer during repeat instruction execution Time from interrupt exception handling (SR and PC saves and vector address fetch) until fetch of first instruction of exception service routine starts 5.0 × Icyc + m1 + m2 + m3 5.0 × Icyc + m1 + m2 + m3 5.0 × Icyc + m1 + m2 + m3 5.0 × Icyc + m1 + m2 + m3 Response time Total: X + 7.0 × Icyc + m1 + m2 + m3 X + 5.5 × Icyc + 1.0 × Ecyc + 1.5 × Pcyc + m1 + m2 + m3 X + 5.5 × Icyc + 1.0 × Pcyc + m1 + m2 + m3 X + 5.0 × Icyc + 1.0 × Pcyc + m1 + m2 + m3 Minimum: 10 11 9.5 9 I φ:Eφ:Pφ = 1:1:1 Maximum: 11 + 2 (m1 + m2 + m3) + m4 19.5 + 2 (m1 + m2 + m3) + m4 13.5 + 2 (m1 + m2 + m3) + m4 13.0 + 2 (m1 + m2 + m3) + m4 I φ:Eφ:Pφ = 1:1/4:1/4 Notes: m1–m4 are the number of states needed for the following memory accesses m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch of first instruction of interrupt service routine Icyc: I φ cycle time Ecyc: E φ cycle time Pcyc: P φ cycle time Peripheral modules A: DMAC, REF (BSC) Peripheral modules B: WDT, FRT, TPU, SCIF, SIOF, SIO, E-DMAC |
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