SH7616 datasheet(212/935 Pages) RENESAS

212 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 186 of 906

REJ09B0292-0200

Bits

14–8

6–0

Vector number setting register R

Receive overrun error interrupt

(SIO1)

Transmit underrun error

interrupt (SIO1)

Vector number setting register S

Receive-data-full interrupt

(SIO1)

Transmit-data-empty interrupt

(SIO1)

Vector number setting register T

Receive overrun error interrupt

(SIO2)

Transmit underrun error

interrupt (SIO2)

Vector number setting register U

Receive-data-full interrupt

(SIO2)

Transmit-data-empty interrupt

(SIO2)

As table 5.6 shows, two on-chip peripheral module interrupts are assigned to each register. Set the

vector numbers by setting the corresponding 7-bit groups (bits 14 to 8 and bits 6 to 0) with values

in the range of H'00 (0000000) to H'7F (1111111). H'00 is vector number 0 (the lowest); H'7F is

vector number 127 (the highest). The vector table address is calculated by the following equation.

Vector table address = VBR + (vector number

× 4)

A reset initializes a vector number setting register to H'0000. They are not initialized in standby

mode.

Table 5.7

Interrupt Request Sources and Vector Number Setting Registers (2)

Setting Function

Vector number setting register DMA0

(VCRDMA0)

Channel 0 transfer end interrupt for DMAC

Vector number setting register DMA1

(VCRDMA1)

Channel 1 transfer end interrupt for DMAC

As shown in table 5.7 the vector numbers for direct memory access controller transfer-end

interrupts are set in VCRDMA0 and VCRDMA1. See sections 11, Direct Memory Access

Controller, for more details.

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